PIC24FJ64GA705 Datasheet, PDF (80/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 7-1: RCON: RESET CONTROL REGISTER
R/W-0
R/W-0
R/W-1
R/W-0
U-0
TRAPR⁽¹⁾ IOPUWR⁽¹⁾ SBOREN⁽⁵⁾ RETEN⁽²⁾
—
bit 15
R/W-0
EXTR⁽¹⁾
bit 7
R/W-0
SWR⁽¹⁾
R/W-0
SWDTEN⁽⁴⁾
R/W-0
WDTO⁽¹⁾
R/W-0
SLEEP⁽¹⁾
U-0
—
R/W-0
IDLE⁽¹⁾
R/W-0
CM⁽¹⁾
R/W-1
BOR⁽¹⁾
R/W-0
VREGS⁽³⁾
bit 8
R/W-1
POR⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
bit 8
bit 7
bit 6
TRAPR: Trap Reset Flag bit⁽¹⁾
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit⁽¹⁾
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an
Address Pointer and caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
SBOREN: Software Control Over the BOR Function bit⁽⁵⁾
1 = BOR is enabled
0 = BOR is disabled
RETEN: Retention Mode Enable bit⁽²⁾
1 = Retention mode is enabled while device is in Sleep mode (1.2V regulator supplies to the core)
0 = Retention mode is disabled; normal voltage levels are present
Unimplemented: Read as ‘0’
CM: Configuration Word Mismatch Reset Flag bit⁽¹⁾
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
VREGS: Fast Wake-up from Sleep bit⁽³⁾
1 = Fast wake-up is disabled (lower power)
0 = Fast wake-up is enabled (higher power)
EXTR: External Reset (MCLR) Pin bit⁽¹⁾
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software RESET (Instruction) Flag bit⁽¹⁾
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
Note 1:
2:
3:
4:
5:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN
bit has no effect. Retention mode preserves the SRAM contents during Sleep.
Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep.
Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.
If the FWDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
The BOREN<1:0> (FPOR<1:0>) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.
DS30010118B-page 80
 2016 Microchip Technology Inc.