PIC24FJ64GA705 Datasheet, PDF (135/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 11-12: IOCPDx: INTERRUPT-ON-CHANGE PULL-DOWN ENABLE x REGISTER⁽¹⁾
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
IOCPDx<15:8>
R/W-0
R/W-0
U-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
IOCPDx<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
IOCPDx<15:0>: Interrupt-on-Change Pull-Down Enable x bits
1 = Pull-down is enabled
0 = Pull-down is disabled
Note 1: See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
 2016 Microchip Technology Inc.
DS30010118B-page 135