PIC24FJ64GA705 Datasheet, PDF (141/412 Pages) –

PIC24FJ256GA705 FAMILY
11.5.6
PERIPHERAL PIN SELECT
REGISTERS
The PIC24FJ256GA705 family of devices implements
a total of 34 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (19)
• Output Remappable Peripheral Registers (15)
Note:
Input and Output register values can only
be changed if IOLOCK (OSCCON<6>) = 0.
See Section 11.5.4.1 “Control Register
Lock” for a specific command sequence.
REGISTER 11-13: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
bit 15
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
R/W-1
INT1R0
bit 8
U-0
—
bit 7
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
OCTRIG1R5 OCTRIG1R4 OCTRIG1R3 OCTRIG1R2 OCTRIG1R1 OCTRIG1R0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
OCTRIG1R<5:0>: Assign Output Compare Trigger 1 to Corresponding RPn or RPIn Pin bits
REGISTER 11-14: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
bit 15
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
R/W-1
INT3R0
bit 8
U-0
—
bit 7
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits
 2016 Microchip Technology Inc.
DS30010118B-page 141