PIC24FJ64GA705 Datasheet, PDF (192/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-2: CCPxCON1H: CCPx CONTROL 1 HIGH REGISTERS
R/W-0
R/W-0
U-0
OPSSRC⁽¹⁾ RTRGEN⁽²⁾
—
bit 15
U-0
R/W-0
R/W-0
—
OPS3⁽³⁾
OPS2⁽³⁾
R/W-0
OPS1⁽³⁾
R/W-0
OPS0⁽³⁾
bit 8
R/W-0
TRIGEN
bit 7
R/W-0
ONESHOT
R/W-0
ALTSYNC
R/W-0
SYNC4
R/W-0
SYNC3
R/W-0
SYNC2
R/W-0
SYNC1
R/W-0
SYNC0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-12
bit 11-8
bit 7
bit 6
bit 5
bit 4-0
OPSSRC: Output Postscaler Source Select bit⁽¹⁾
1 = Output postscaler scales module trigger output events
0 = Output postscaler scales time base interrupt events
RTRGEN: Retrigger Enable bit⁽²⁾
1 = Time base can be retriggered when the TRIGEN bit = 1
0 = Time base may not be retriggered when the TRIGEN bit = 1
Unimplemented: Read as ‘0’
OPS3<3:0>: CCPx Interrupt Output Postscale Select bits⁽³⁾
1111 = Interrupt every 16th time base period match
1110 = Interrupt every 15th time base period match
...
0100 = Interrupt every 5th time base period match
0011 = Interrupt every 4th time base period match or 4th input capture event
0010 = Interrupt every 3rd time base period match or 3rd input capture event
0001 = Interrupt every 2nd time base period match or 2nd input capture event
0000 = Interrupt after each time base period match or input capture event
TRIGEN: CCPx Trigger Enable bit
1 = Trigger operation of time base is enabled
0 = Trigger operation of time base is disabled
ONESHOT: One-Shot Mode Enable bit
1 = One-Shot Trigger mode is enabled; Trigger mode duration is set by OSCNT<2:0>
0 = One-Shot Trigger mode is disabled
ALTSYNC: CCPx Clock Select bit
1 = An alternate signal is used as the module synchronization output signal
0 = The module synchronization output signal is the Time Base Reset/rollover event
SYNC<4:0>: CCPx Synchronization Source Select bits
See Table 16-5 for the definition of inputs.
Note 1:
2:
3:
This control bit has no function in Input Capture modes.
This control bit has no function when TRIGEN = 0.
Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
DS30010118B-page 192
 2016 Microchip Technology Inc.