PIC24FJ64GA705 Datasheet, PDF (243/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 20-2: PMCON2: EPMP CONTROL REGISTER 2
R-0, HSC
U-0
R/C-0, HS R/C-0, HS
U-0
U-0
U-0
U-0
BUSY
—
ERROR TIMEOUT
—
—
—
—
bit 15
bit 8
R/W-0
RADDR23⁽¹⁾
bit 7
R/W-0
RADDR22⁽¹⁾
R/W-0
RADDR21⁽¹⁾
R/W-0
RADDR20⁽¹⁾
R/W-0
RADDR19⁽¹⁾
R/W-0
RADDR18⁽¹⁾
R/W-0
RADDR17⁽¹⁾
R/W-0
RADDR16⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
HSC = Hardware Settable/Clearable bit
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7-0
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
Unimplemented: Read as ‘0’
ERROR: Error bit
1 = Transaction error (illegal transaction was requested)
0 = Transaction completed successfully
TIMEOUT: Time-out bit
1 = Transaction timed out
0 = Transaction completed successfully
Unimplemented: Read as ‘0’
RADDR<23:16>: Parallel Master Port Reserved Address Space bits⁽¹⁾
Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh.
 2016 Microchip Technology Inc.
DS30010118B-page 243