PIC24FJ64GA705 Datasheet, PDF (178/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
—
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
OCSIDL
OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2⁽²⁾
R/W-0
ENFLT1⁽²⁾
bit 8
R/W-0
ENFLT0⁽²⁾
bit 7
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0
OCFLT2^(2,3) OCFLT1^(2,4) OCFLT0^(2,4) TRIGMODE
R/W-0
OCM2⁽¹⁾
R/W-0
OCM1⁽¹⁾
R/W-0
OCM0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as ‘0’
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL<2:0>: Output Compare x Timer Select bits
111 = Peripheral clock (FCY)
110 = Reserved
101 = Reserved
100 = Timer1 clock (only synchronous clock is supported)
011 = Unimplemented
010 = Unimplemented
001 = Timer3 clock
000 = Timer2 clock
ENFLT2: Fault Input 2 Enable bit⁽²⁾
1 = Fault 2 (Comparator 1/2/3 out) is enabled⁽³⁾
0 = Fault 2 is disabled
ENFLT1: Fault Input 1 Enable bit⁽²⁾
1 = Fault 1 (OCFB pin) is enabled⁽⁴⁾
0 = Fault 1 is disabled
ENFLT0: Fault Input 0 Enable bit⁽²⁾
1 = Fault 0 (OCFA pin) is enabled⁽⁴⁾
0 = Fault 0 is disabled
OCFLT2: Output Compare x PWM Fault 2 (Comparator 1/2/3) Condition Status bit^(2,3)
1 = PWM Fault 2 has occurred
0 = No PWM Fault 2 has occurred
OCFLT1: Output Compare x PWM Fault 1 (OCFB pin) Condition Status bit^(2,4)
1 = PWM Fault 1 has occurred
0 = No PWM Fault 1 has occurred
OCFLT0: PWM Fault 0 (OCFA pin) Condition Status bit^(2,4)
1 = PWM Fault 0 has occurred
0 = No PWM Fault 0 has occurred
Note 1:
2:
3:
4:
The OCx output must also be configured to an available RPn pin. For more information, see Section 11.5
“Peripheral Pin Select (PPS)”.
The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110.
The Comparator 1 output controls the OC1-OC3 channels.
The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.5 “Peripheral Pin Select (PPS)”.
DS30010118B-page 178
 2016 Microchip Technology Inc.