PIC24FJ64GA705 Datasheet, PDF (36/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
EDS and Table
Data Access
Control Block
Interrupt
Controller
Data Bus
16
8
16
16
Data Latch
23
23
PCH
PCL
Program Counter
Data RAM
Up to 0x7FFF
16
Stack
Control
Logic
Loop
Control
Logic
Address
Latch
23
16
Address Latch
Program Memory/
Extended Data
Space
Data Latch
Address Bus
24
RAGU
WAGU
ROM Latch
EA MUX
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
Divide
Support
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1: CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
PC
SR
SPLIM
TBLPAG
RCOUNT
CORCON
DISICNT
DSRPAG
DSWPAG
Working Register Array
23-Bit Program Counter
ALU STATUS Register
Stack Pointer Limit Value Register
Table Memory Page Address Register
REPEAT Loop Counter Register
CPU Control Register
Disable Interrupt Count Register
Data Space Read Page Register
Data Space Write Page Register
DS30010118B-page 36
 2016 Microchip Technology Inc.