PIC24FJ64GA705 Datasheet, PDF(218/412 Page) –

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PIC24FJ64GA705 Datasheet, PDF (218/412 Pages) –

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PIC24FJ256GA705 FAMILY

FIGURE 17-3:

SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

Processor 1 (SPIx Master)

SDOx

Serial Receive FIFO

(SPIxRXB)(2)

Processor 2 (SPIx Slave)

SDIx

Serial Transmit FIFO

(SPIxTXB)(2)

Shift Register

(SPIxRXSR)

MSb

LSb

Shift Register

(SPIxTXSR)

MSb

LSb

SDIx

SDOx

SDOx

Shift Register

(SPIxTXSR)

SDIx MSb

LSb

Shift Register

(SPIxRXSR)

MSb

LSb

Serial Transmit FIFO

(SPIxTXB)(2)

SPIx Buffer

(SPIxBUF)

SCKx Serial Clock

SCKx Serial Receive FIFO

(SPIxRXB)(2)

SSx(1)

SPIx Buffer

(SPIxBUF)

MSTEN (SPIxCON1L<5>) = 1

MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers

are memory-mapped to SPIxBUF.

DS30010118B-page 218

ï£ 2016 Microchip Technology Inc.

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