PIC24FJ64GA705 Datasheet, PDF (137/412 Pages) –

PIC24FJ256GA705 FAMILY
11.5.3.1 Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-13
through Register 11-31).
Each register contains one or two sets of 6-bit fields,
with each set associated with one of the pin-selectable
peripherals. Programming a given peripheral’s bit field
with an appropriate 6-bit value maps the RPn/RPIn pin
with that value to that peripheral. For any given device,
the valid range of values for any of the bit fields corre-
sponds to the maximum number of Peripheral Pin
Selections supported by the device.
TABLE 11-6: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)⁽¹⁾
Input Name
Function Name
Register
Output Compare Trigger 1
OCTRIG1
RPINR0<5:0>
External Interrupt 1
INT1
RPINR0<13:8>
External Interrupt 2
INT2
RPINR1<5:0>
External Interrupt 3
INT3
RPINR1<13:8>
External Interrupt 4
INT4
RPINR2<5:0>
Output Compare Trigger 2
OCTRIG2
RPINR2<13:8>
Timer2 External Clock
T2CK
RPINR3<5:0>
Timer3 External Clock
T3CK
RPINR3<13:8>
Input Capture 1
ICM1
RPINR5<5:0>
Input Capture 2
ICM2
RPINR5<13:8>
Input Capture 3
ICM3
RPINR6<5:0>
Input Capture 4
ICM4
RPINR6<13:8>
Input Capture 1
IC1
RPINR7<5:0>
Input Capture 2
IC2
RPINR7<13:8>
Input Capture 3
IC3
RPINR8<5:0>
Output Compare Fault A
OCFA
RPINR11<5:0>
Output Compare Fault B
OCFB
RPINR11<13:8>
CCP Clock Input A
TCKIA
RPINR12<5:0>
CCP Clock Input B
TCKIB
RPINR12<13:8>
UART1 Receive
U1RX
RPINR18<5:0>
UART1 Clear-to-Send
U1CTS
RPINR18<13:8>
UART2 Receive
U2RX
RPINR19<5:0>
UART2 Clear-to-Send
U2CTS
RPINR19<13:8>
SPI1 Data Input
SDI1
RPINR20<5:0>
SPI1 Clock Input
SCK1IN
RPINR20<13:8>
SPI1 Slave Select Input
SS1IN
RPINR21<5:0>
SPI2 Data Input
SDI2
RPINR22<5:0>
SPI2 Clock Input
SCK2IN
RPINR22<13:8>
SPI2 Slave Select Input
SS2IN
RPINR23<5:0>
Generic Timer External Clock
TxCK
RPINR23<13:8>
CLC Input A
CLCINA
RPINR25<5:0>
CLC Input B
CLCINB
RPINR25<13:8>
SPI3 Data Input
SDI3
RPINR28<5:0>
SPI3 Clock Input
SCK3IN
RPINR28<13:8>
SPI3 Slave Select Input
SS3IN
RPINR29<5:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.
Function Mapping
Bits
OCTRIG1R<5:0>
INT1R<5:0>
INT2R<5:0>
INT3R<5:0>
INT4R<5:0>
OCTRIG2R<5:0>
T2CKR<5:0>
T3CKR<5:0>
ICM1R<5:0>
ICM2R<5:0>
ICM3R<5:0>
ICM4R<5:0>
IC1R<5:0>
IC2R<5:0>
IC3R<5:0>
OCFAR<5:0>
OCFBR<5:0>
TCKIAR<5:0>
TCKIBR<5:0>
U1RXR<5:0>
U1CTSR<5:0>
U2RXR<5:0>
U2CTSR<5:0>
SDI1R<5:0>
SCK1R<5:0>
SS1R<5:0>
SDI2R<5:0>
SCK2R<5:0>
SS2R<5:0>
TXCKR<5:0>
CLCINAR<5:0>
CLCINBR<5:0>
SDI3R<5:0>
SCK3R<5:0>
SS3R<5:0>
 2016 Microchip Technology Inc.
DS30010118B-page 137