PIC24FJ64GA705 Datasheet, PDF (96/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 8-6:
R-0
CPUIRQ
bit 15
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
R/W-0
U-0
—
VHOLD
—
R-0
ILR3
R-0
ILR2
R-0
ILR1
R-0
ILR0
bit 8
R-0
VECNUM7
bit 7
R-0
R-0
R-0
R-0
VECNUM6 VECNUM5 VECNUM4 VECNUM3
R-0
VECNUM2
R-0
VECNUM1
R-0
VECNUM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7-0
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0 = No interrupt request is unacknowledged
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1 = The VECNUMx bits contain the value of the highest priority pending interrupt
0 = The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt
that has occurred with higher priority than the CPU, even if other interrupts are pending)
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
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•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
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00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000111 = 7, Reserved; do not use
00000110 = 6, Generic soft error trap
00000101 = 5, Reserved; do not use
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap
DS30010118B-page 96
 2016 Microchip Technology Inc.