PIC24FJ64GA705 Datasheet, PDF (39/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/C-0
R/W-1
U-0
U-0
—
—
—
—
IPL3⁽¹⁾
PSV⁽²⁾
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
PSV: Program Space Visibility (PSV) in Data Space Enable⁽²⁾
1 = Program space is visible in Data Space
0 = Program space is not visible in Data Space
Unimplemented: Read as ‘0’
Note 1:
2:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level;
see Register 3-1 for bit description.
If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of
reading from the PSV section of program memory. This bit is not individually addressable.
 2016 Microchip Technology Inc.
DS30010118B-page 39