PIC24FJ64GA705 Datasheet, PDF (241/412 Pages) –

PIC24FJ256GA705 FAMILY
TABLE 20-2: ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS
Pin Name
(Alternate Function)
Type
Description
PMA<22:16>
O
Address Bus bits<22:16>
PMA14
O
Address Bus bit 14
I/O
Data Bus bit 14 (16-bit port with Multiplexed Addressing)
(PMCS1)
O
Chip Select 1 (alternate location)
PMA<13:8>
O
Address Bus bits<13:8>
I/O
Data Bus bits<13:8> (16-bit port with Multiplexed Addressing)
PMA<7:3>
O
Address Bus bits<7:3>
PMA2
(PMALU)
O
Address Bus bit 2
O
Address Latch Upper Strobe for Multiplexed Address
PMA1
(PMALH)
I/O
Address Bus bit 1
O
Address Latch High Strobe for Multiplexed Address
PMA0
(PMALL)
I/O
Address Bus bit 0
O
Address Latch Low Strobe for Multiplexed Address
PMD<15:8>
I/O
Data Bus bits<15:8> (Demultiplexed Addressing)
PMD<7:4>
I/O
Data Bus bits<7:4>
O
Address Bus bits<7:4> (4-bit port with 1-Phase Multiplexed Addressing)
PMD<3:0>
I/O
Data Bus bits<3:0>
PMCS1
O
Chip Select 1
PMCS2
O
Chip Select 2
PMWR
I/O
Write Strobe⁽¹⁾
(PMENB)
I/O
Enable Signal⁽¹⁾
PMRD
I/O
Read Strobe⁽¹⁾
(PMRD/PMWR)
I/O
Read/Write Signal⁽¹⁾
PMBE1
O
Byte Indicator
PMBE0
O
Nibble or Byte Indicator
PMACK1
I
Acknowledgment Signal 1
PMACK2
I
Acknowledgment Signal 2
Note 1: Signal function depends on the setting of the MODE<1:0> and SM bits (PMCON1<9:8> and
PMCSxCF<8>).
 2016 Microchip Technology Inc.
DS30010118B-page 241