PIC24FJ64GA705 Datasheet, PDF (44/412 Pages) –

PIC24FJ256GA705 FAMILY
4.1.4
CODE-PROTECT CONFIGURATION
BITS
The device implements intermediate security features
defined by the FSEC register. The Boot Segment (BS)
is the higher privileged segment and the General Seg-
ment (GS) is the lower privileged segment. The total
user code memory can be split into BS or GS. The size
of the segments is determined by the BSLIM<12:0>
bits. The relative location of the segments within user
space does not change, such that BS (if present) occu-
pies the memory area just after the Interrupt Vector
Table (IVT) and the GS occupies the space just after
the BS (or if the Alternate IVT is enabled, just after it).
The Configuration Segment (CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that is loaded by the NVM Controller during the
Reset sequence.
4.1.5 CUSTOMER OTP MEMORY
PIC24FJ256GA705 family devices provide 256 bytes of
One-Time-Programmable (OTP) memory, located at
addresses, 801700h through 8017FEh. This memory
can be used for persistent storage of application-specific
information that will not be erased by reprogramming the
device. This includes many types of information, such as
(but not limited to):
• Application Checksums
• Code Revision Information
• Product Information
• Serial Numbers
• System Manufacturing Dates
• Manufacturing Lot Numbers
Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data is not cleared by a chip erase.
Note:
Do not write the OTP memory more than
one time. Writing to the OTP memory
more than once may result in a permanent
ECC Double-Bit Error (ECCDBE) trap.
DS30010118B-page 44
 2016 Microchip Technology Inc.