PIC24FJ64GA705 Datasheet, PDF (343/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 29-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN<1:0>
WDTCLKS<1:0>
SOSC
FRC
Peripheral Clock
LPRC
WINDIS
System Clock (LRPC)
LPRC Control
FWPSA
31 kHz
Prescaler
(5-bit/7-bit)
WDT
Counter
1 ms/4 ms
All Device Resets
Transition to New
Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
WDTPS<3:0>
Postscaler
1:1 to 1:32.768
Sleep or Idle Mode
Wake from
Sleep
WDT Overflow
Reset
 2016 Microchip Technology Inc.
DS30010118B-page 343