PIC24FJ64GA705 Datasheet, PDF (108/412 Pages) –

PIC24FJ256GA705 FAMILY
9.5 Oscillator Modes
The PLL block is shown in Figure 9-2. In this system,
the input from the Primary Oscillator is divided down by
a PLL prescaler to generate a 4 MHz output. This is
used to drive an on-chip, 96 MHz PLL frequency multi-
plier to drive the fixed, divide-by-3 frequency divider
and configurable PLL prescaler/divider to generate a
range of system clock frequencies. The CPDIV<1:0>
bits select the system clock speed. Available clock
options are listed in Table 9-2.
The user must manually configure the PLL divider to
generate the required 4 MHz output using the
PLLMODE<3:0> Configuration bits. This limits the
choices for Primary Oscillator frequency to a total of
eight possibilities, as shown in Table 9-3.
TABLE 9-2: SYSTEM CLOCK OPTIONS
MCU Clock Division
(CPDIV<1:0>)
Microcontroller
Clock Frequency
None (00)
2 (01)
4 (10)
8 (11)
32 MHz
16 MHz
8 MHz
4 MHz
TABLE 9-3: VALID PRIMARY OSCILLATOR
CONFIGURATIONS
Input Oscillator
Frequency
Clock Mode
PLL Mode
(PLLMODE<3:0>)
48 MHz
32 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
4 MHz
ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
ECPLL, XTPLL,
FRCPLL
ECPLL, XTPLL,
FRCPLL
12 (0111)
8 (0110)
6 (0101)
5 (0100)
4 (0011)
3 (0010)
2 (0001)
1 (0000)
FIGURE 9-2:
PLL BLOCK
(Note 1)
Input from
POSC
Input from
FRC
PLLMODE<3:0>
 12
8
6
5
4
3
2
1
0111
0110
0101
0100 4 MHz
0011
0010
0001
0000
96 MHz
PLL
32 MHz
3
8
4
11 _{PLL Output}
10 for System Clock
 2 ₀₁
 1 ₀₀
CPDIV<1:0>
x4
1100
x6
1101
x8
1110
Note 1: This MUX is controlled by the COSC<2:0> bits when running from the PLL or the NOSC<2:0> bits when
preparing to switch to the PLL.
DS30010118B-page 108
 2016 Microchip Technology Inc.