PIC24FJ64GA705 Datasheet, PDF (240/412 Pages) –

PIC24FJ256GA705 FAMILY
20.1 Memory Addressable in Different
Modes
The memory space addressable by the device
depends on the address/data multiplexing selection; it
varies from 1K to 2 MB. Refer to Table 20-1 for different
Memory-Addressable modes.
20.3 PMDIN1 and PMDIN2 Registers
The EPMP Data Input 1 and Data Input 2 registers are
used in Slave modes to buffer incoming data. These
registers hold data that is asynchronously clocked in. In
Master mode, PMDIN1 is the holding register for
incoming data.
20.2 PMDOUT1 and PMDOUT2
Registers
The EPMP Data Output 1 and Data Output 2 registers
are used only in Slave mode. These registers act as a
buffer for outgoing data.
TABLE 20-1: EPMP FEATURE DIFFERENCES BY DEVICE PIN COUNT
Data Port Size
PMA<9:8>
PMA<7:0>
PMD<7:4>
PMD<3:0>
8-Bit (PTSZ<1:0> = 00)
4-Bit (PTSZ<1:0> = 01)
8-Bit (PTSZ<1:0> = 00)
4-Bit (PTSZ<1:0> = 01)
8-Bit (PTSZ<1:0> = 00)
4-Bit (PTSZ<1:0> = 01)
8-Bit (PTSZ<1:0> = 00)
4-Bit (PTSZ<1:0> = 01)
Demultiplexed Address (ADRMUX<1:0> = 00)
Addr<9:8>
Addr<7:0>
Data
Addr<9:8>
Addr<7:0>
—
Data
1 Address Phase (ADRMUX<1:0> = 01)
—
PMALL
Addr<7:0> Data
Addr<9:8>
PMALL
Addr<7:4>
Addr<3:0>
—
Data (1)
2 Address Phases (ADRMUX<1:0> = 10)
—
PMALL
Addr<7:0>
PMALH
Addr<15:8>
—
Data
Addr<9:8>
PMALL
Addr<3:0>
PMALH
Addr<7:4>
—
Data
3 Address Phases (ADRMUX<1:0> = 11)
—
PMALL
Addr<7:0>
PMALH
Addr<15:8>
PMALU
Addr<22:16>
—
Data
Addr<13:12>
PMALL
Addr<3:0>
PMALH
Addr<7:4>
PMALU
Addr<11:8>
—
Data
Accessible Memory
1K
1K
1K
1K
64K
1K
2 Mbytes
16K
DS30010118B-page 240
 2016 Microchip Technology Inc.