PIC24FJ64GA705 Datasheet, PDF (205/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 17-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CKE: SPIx Clock Edge Select bit⁽¹⁾
1 = Transmit happens on transition from active clock state to Idle clock state
0 = Transmit happens on transition from Idle clock state to active clock state
SSEN: Slave Select Enable bit (Slave mode)⁽²⁾
1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the slave select input
0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O)
CKP: SPIx Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
DISSDI: Disable SDIx Input Port bit
1 = SDIx pin is not used by the module; pin is controlled by the port function
0 = SDIx pin is controlled by the module
DISSCK: Disable SCKx Output Port bit
1 = SCKx pin is not used by the module; pin is controlled by the port function
0 = SCKx pin is controlled by the module
MCLKEN: Master Clock Enable bit⁽³⁾
1 = MCLK is used by the BRG
0 = PBCLK is used by the BRG
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
ENHBUF: Enhanced Buffer Mode Enable bit
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1:
2:
3:
4:
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
When FRMEN = 1, SSEN is not used.
MCLKEN can only be written when the SPIEN bit = 0.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
 2016 Microchip Technology Inc.
DS30010118B-page 205