PIC24FJ64GA705 Datasheet, PDF (225/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 18-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 8
SMEN: SMBus Input Levels Enable bit
1 = Enables input logic so thresholds are compliant with the SMBus specification
0 = Disables SMBus-specific inputs
bit 7
GCEN: General Call Enable bit (I²C Slave mode only)
1 = Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception
0 = General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit
In I²C Slave mode only; used in conjunction with the SCLREL bit.
1 = Enables clock stretching
0 = Disables clock stretching
bit 5
ACKDT: Acknowledge Data bit
In I²C Master mode during Master Receive mode. The value that will be transmitted when the user
initiates an Acknowledge sequence at the end of a receive.
In I²C Slave mode when AHEN = 1 or DHEN = 1. The value that the slave will transmit when it initiates
an Acknowledge sequence at the end of an address or data reception.
1 = NACK is sent
0 = ACK is sent
bit 4
ACKEN: Acknowledge Sequence Enable bit
In I²C Master mode only; applicable during Master Receive mode.
1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits the ACKDT data bit
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (I²C Master mode only)
1 = Enables Receive mode for I²C; automatically cleared by hardware at the end of the 8-bit receive
data byte
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (I²C Master mode only)
1 = Initiates Stop condition on the SDAx and SCLx pins
0 = Stop condition is Idle
bit 1
RSEN: Restart Condition Enable bit (I²C Master mode only)
1 = Initiates Restart condition on the SDAx and SCLx pins
0 = Restart condition is Idle
bit 0
SEN: Start Condition Enable bit (I²C Master mode only)
1 = Initiates Start condition on the SDAx and SCLx pins
0 = Start condition is Idle
Note 1:
2:
Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end
of slave reception. The user software must provide a delay between writing to the transmit buffer and set-
ting the SCLREL bit. This delay must be greater than the minimum setup time for slave transmissions, as
specified in Section 32.0 “Electrical Characteristics”.
Automatically cleared to ‘0’ at the beginning of slave transmission.
 2016 Microchip Technology Inc.
DS30010118B-page 225