PIC24FJ64GA705 Datasheet, PDF (404/412 Pages) –

PIC24FJ256GA705 FAMILY
Product Identification System............................................ 409
Program Memory Space
Access Using Table Instructions ................................. 60
Addressing .................................................................. 58
Configuration Bits
Code-Protect....................................................... 44
Overview ............................................................. 43
Configuration Word Addresses ................................... 43
Customer OTP Memory .............................................. 44
Hard Memory Vectors ................................................. 43
Memory Map ............................................................... 42
Organization................................................................ 43
Reading Data Using EDS ........................................... 61
Sizes and Boundaries ................................................. 42
Program Verification.......................................................... 344
Pulse-Width Modulation (PWM) Mode .............................. 175
Pulse-Width Modulation. See PWM.
PWM
Duty Cycle and Period .............................................. 176
R
Real-Time Clock and Calendar (RTCC)............................ 251
Reference Clock Output.................................................... 109
Referenced Sources ........................................................... 13
Register Summary
Peripheral Module Disable (PMD) ............................ 116
Registers
AD1CHITL (A/D Scan Compare Hit, Low Word ........ 302
AD1CHS (A/D Sample Select) .................................. 300
AD1CON1 (A/D Control 1) ........................................ 293
AD1CON2 (A/D Control 2) ........................................ 295
AD1CON3 (A/D Control 3) ........................................ 297
AD1CON4 (A/D Control 4) ........................................ 298
AD1CON5 (A/D Control 5) ........................................ 299
AD1CSSH (A/D Input Scan Select, High Word) ....... 303
AD1CSSL (A/D Input Scan Select, Low Word) ......... 303
AD1CTMENH (A/D CTMU Enable, High Word)........ 304
AD1CTMENL (A/D CTMU Enable, Low Word) ......... 304
ALMDATEH (RTCC Alarm Date High)...................... 263
ALMDATEL (RTCC Alarm Date Low) ....................... 263
ALMTIMEH (RTCC Alarm Time High) ...................... 262
ALMTIMEL (RTCC Alarm Time Low)........................ 262
ANCFG (A/D Band Gap Reference
Configuration) ................................................... 301
ANSELx (Analog Select for PORTx) ......................... 132
CCPxCON1H (CCPx Control 1 High) ....................... 192
CCPxCON1L (CCPx Control 1 Low)......................... 190
CCPxCON2H (CCPx Control 2 High) ....................... 195
CCPxCON2L (CCPx Control 2 Low)......................... 194
CCPxCON3H (CCPx Control 3 High) ....................... 197
CCPxCON3L (CCPx Control 3 Low)......................... 196
CCPxSTATH (CCPx Status High) ............................ 199
CCPxSTATL (CCPx Status Low) .............................. 198
CLCxCONH (CLCx Control High) ............................. 281
CLCxCONL (CLCx Control Low) .............................. 280
CLCxGLSH (CLCx Gate Logic Input
Select High) ...................................................... 285
CLCxGLSL (CLCx Gate Logic Input
Select Low) ....................................................... 283
CLCxSEL (CLCx Input MUX Select) ......................... 282
CLKDIV (Clock Divider) ............................................ 102
CMSTAT (Comparator Module Status) ..................... 313
CMxCON (Comparator x Control,
Comparators 1 Through 3)................................ 312
CORCON (CPU Core Control).............................. 39, 92
CRCCON1 (CRC Control 1) ..................................... 274
DS30010118B-page 404
CRCCON2 (CRC Control 2) ..................................... 275
CRCXORH (CRC XOR Polynomial, High Byte) ....... 276
CRCXORL (CRC XOR Polynomial, Low Byte)......... 276
CTMUCON1H (CTMU Control 1 High) ..................... 323
CTMUCON1L (CTMU Control 1 Low) ...................... 321
CTMUCON2L (CTMU Control 2 Low) ...................... 325
CVRCON (Comparator Voltage
Reference Control) ........................................... 316
DATEH (RTCC Date High) ....................................... 261
DATEL (RTCC Date Low)......................................... 261
DMACHn (DMA Channel n Control) ........................... 68
DMACON (DMA Engine Control)................................ 67
DMAINTn (DMA Channel n Interrupt)......................... 69
FBSLIM Configuration .............................................. 331
FDEVOPT1 Configuration ........................................ 339
FICD Configuration ................................................... 338
FOSC Configuration ................................................. 334
FOSCSEL Configuration........................................... 333
FPOR Configuration ................................................. 337
FSEC Configuration.................................................. 330
FSIGN Configuration ................................................ 332
FWDT Configuration ................................................. 335
HLVDCON (High/Low-Voltage Detect Control) ........ 328
I2CxCONH (I2Cx Control High) ................................ 226
I2CxCONL (I2Cx Control Low) ................................. 224
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 228
I2CxSTAT (I2Cx Status) ........................................... 227
ICxCON1 (Input Capture x Control 1)....................... 169
ICxCON2 (Input Capture x Control 2)....................... 170
INTCON1 (Interrupt Control 1).................................... 93
INTCON2 (Interrupt Control 2).................................... 94
INTCON4 (Interrupt Control 4).................................... 95
INTTREG (Interrupt Control and Status) .................... 96
IOCFx (Interrupt-on-Change Flag x)......................... 134
IOCNx (Interrupt-on-Change Negative Edge x)........ 133
IOCPDx (Interrupt-on-Change Pull-Down
Enable x) .......................................................... 135
IOCPUx (Interrupt-on-Change Pull-up
Enable x) .......................................................... 134
IOCPx (Interrupt-on-Change Positive Edge x).......... 133
IOCSTAT (Interrupt-on-Change Status) ................... 129
LATx (Output Data for PORTx)................................. 131
NVMCON (Flash Memory Control) ............................. 73
OCxCON1 (Output Compare x Control 1) ................ 178
OCxCON2 (Output Compare x Control 2) ................ 180
ODCx (Open-Drain Enable for PORTx).................... 131
OSCCON (Oscillator Control) ................................... 100
OSCDIV (Oscillator Divisor)...................................... 104
OSCFDIV (Oscillator Fractional Divisor)................... 105
OSCTUN (FRC Oscillator Tune)............................... 103
PADCON (Pad Configuration Control)...................... 250
PADCON (Port Configuration) .................................. 129
PMCON1 (EPMP Control 1) ..................................... 242
PMCON2 (EPMP Control 2) ..................................... 243
PMCON3 (EPMP Control 3) ..................................... 244
PMCON4 (EPMP Control 4) ..................................... 245
PMCSxBS (EPMP Chip Select x Base Address)...... 247
PMCSxCF (EPMP Chip Select x Configuration)....... 246
PMCSxMD (EPMP Chip Select x Mode) .................. 248
PMD1 (Peripheral Module Disable 1) ....................... 117
PMD2 (Peripheral Module Disable 2) ....................... 118
PMD3 (Peripheral Module Disable 3) ....................... 119
PMD4 (Peripheral Module Disable 4) ....................... 120
PMD5 (Peripheral Module Disable 5) ....................... 121
PMD6 (Peripheral Module Disable 6) ....................... 122
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