PIC24FJ64GA705 Datasheet, PDF (224/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 18-1: I2CxCONL: I2Cx CONTROL REGISTER LOW
R/W-0
I2CEN
bit 15
U-0
HC, R/W-0
R/W-1
R/W-0
R/W-0
—
I2CSIDL SCLREL⁽¹⁾ STRICT
A10M
R/W-0
DISSLW
R/W-0
SMEN
bit 8
R/W-0
GCEN
bit 7
R/W-0
STREN
R/W-0
ACKDT
HC, R/W-0
ACKEN
HC, R/W-0
RCEN
HC, R/W-0
PEN
HC, R/W-0
RSEN
HC, R/W-0
SEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
I2CEN: I2Cx Enable bit (writable from software only)
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I²C pins are controlled by port functions
Unimplemented: Read as ‘0’
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
SCLREL: SCLx Release Control bit (I²C Slave mode only)⁽¹⁾
Module resets and (I2CEN = 0) sets SCLREL = 1.
If STREN = 0:⁽²⁾
1 = Releases clock
0 = Forces clock low (clock stretch)
If STREN = 1:
1 = Releases clock
0 = Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCLx low
STRICT: I2Cx Strict Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced (for reserved addresses, refer to Table 18-2)
In Slave Mode: The device doesn’t respond to reserved address space and addresses falling in
that category are NACKed.
In Master Mode: The device is allowed to generate addresses with reserved address space.
0 = Reserved addressing would be Acknowledged
In Slave Mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master Mode: Reserved.
A10M: 10-Bit Slave Address Flag bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Slew Rate Control Disable bit
1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0 = Slew rate control is enabled for High-Speed mode (400 kHz)
Note 1:
2:
Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end
of slave reception. The user software must provide a delay between writing to the transmit buffer and set-
ting the SCLREL bit. This delay must be greater than the minimum setup time for slave transmissions, as
specified in Section 32.0 “Electrical Characteristics”.
Automatically cleared to ‘0’ at the beginning of slave transmission.
DS30010118B-page 224
 2016 Microchip Technology Inc.