PIC24FJ64GA705 Datasheet, PDF (24/412 Pages) –

PIC24FJ256GA705 FAMILY
TABLE 1-3: PIC24FJ256GA705 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin
Function
Pin Number/Grid Locator
28-Pin SOIC, 28-Pin QFN,
SSOP, SPDIP UQFN
44-Pin
TQFP
48-Pin ^I/O
QFN/TQFP
Input
Buffer
Description
PMD0
—
—
PMD1
—
—
PMD2
—
—
PMD3
—
—
PMD4
—
—
PMD5
—
—
PMD6
—
—
PMD7
—
—
PMRD/PMWR
—
—
PMWR/PMENB
—
—
PWRGT
—
—
PWRLCLK
12
9
Legend:
TTL = TTL input buffer
ANA = Analog level input/output
DIG = Digital input/output
10
11
I/O DIG/ST/ Parallel Master Port Data (Demultiplexed
TTL Master mode) or Address/Data
9
10
I/O DIG/ST/ ^{(Multiplexed Master modes)}
TTL
8
9
I/O DIG/ST/
TTL
1
1
I/O DIG/ST/
TTL
44
48
I/O DIG/ST/
TTL
43
47
I/O DIG/ST/
TTL
42
46
I/O DIG/ST/
TTL
41
45
I/O DIG/ST/
TTL
11
12
I/O DIG/ST/ Parallel Master Port Read Strobe/
TTL Write Strobe
14
15
I/O DIG/ST/ Parallel Master Port Write Strobe/
TTL Enable Strobe
—
—
O
DIG Real-Time Clock Power Control Output
34
37
I
ST Real-Time Clock 50/60 Hz Clock Input
ST = Schmitt Trigger input buffer
I²C = I²C/SMBus input buffer
XCVR = Dedicated Transceiver
DS30010118B-page 24
 2016 Microchip Technology Inc.