PIC24FJ64GA705 Datasheet, PDF (259/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 21-6: RTCSTATL: RTCC STATUS REGISTER (LOW)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
—
bit 7
U-0
R/C-0
U-0
R/C-0
R-0
R-0
R-0
—
ALMEVT
—
TSAEVT⁽¹⁾
SYNC
ALMSYNC HALFSEC⁽²⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ALMEVT: Alarm Event bit
1 = An alarm event has occurred
0 = An alarm event has not occurred
Unimplemented: Read as ‘0’
TSAEVT: Timestamp A Event bit⁽¹⁾
1 = A timestamp event has occurred
0 = A timestamp event has not occurred
SYNC: Synchronization Status bit
1 = TIME registers may change during software read
0 = TIME registers may be read safely
ALMSYNC: Alarm Synchronization Status bit
1 = Alarm registers (ALMTIME and ALMDATE) and Alarm bits (AMASK<3:0>) should not be modified,
and Alarm Control bits (ALRMEN, ALMRPT<7:0>) may change during software read
0 = Alarm registers and Alarm Control bits may be written/modified safely
HALFSEC: Half Second Status bit⁽²⁾
1 = Second half period of a second
0 = First half period of a second
Note 1: User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not
valid until TSAEVT reads as ‘1’.
2: This bit is read-only; it is cleared to ‘0’ on a write to the SECONE<3:0> bits.
 2016 Microchip Technology Inc.
DS30010118B-page 259