PIC24FJ64GA705 Datasheet, PDF (91/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 8-1: SR: ALU STATUS REGISTER⁽¹⁾
U-0
—
bit 15
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0⁽³⁾
R/W-0⁽³⁾
R/W-0⁽³⁾
R-0
IPL2⁽²⁾
IPL1⁽²⁾
IPL0⁽²⁾
RA
bit 7
R/W-0
N
U-0
—
R/W-0
OV
U-0
—
R/W-0
Z
R/W-0
DC
bit 8
R/W-0
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’= Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
2:
3:
For complete register details, see Register 3-1.
The IPL<2:0> Status bits are concatenated with the IPL3 Status bit (CORCON<3>) to form the CPU
Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts
are disabled when IPL3 = 1.
The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
 2016 Microchip Technology Inc.
DS30010118B-page 91