PIC24FJ64GA705 Datasheet, PDF (305/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 24-3:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
Rs ^ANx
AVDD
VT = 0.6V
RIC  250
Sampling
Switch
SS _RSS
VA
CPIN
VT = 0.6V
ILEAKAGE
500 nA
+
S/H
–
CHOLD
= S/H Input Capacitance
= 40 pF
AVSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
Various Junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
CHOLD = Sample/Hold Capacitance
Sampling
Switch
RMAX
(RSS  3 k)
RMIN
AVDDMIN
AVDD (V)
AVDDMAX
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  2.5 k.
EQUATION 24-1: A/D CONVERSION CLOCK PERIOD
TAD = TCY (ADCS + 1)
ADCS =
TAD
TCY
–1
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
 2016 Microchip Technology Inc.
DS30010118B-page 305