PIC24FJ64GA705 Datasheet, PDF (131/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 11-5: LATx: OUTPUT DATA FOR PORTx REGISTER⁽¹⁾
R/W-x
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
LATx<15:8>
R/W-x
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
LATx<7:0>
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
LATx<15:0>: PORTx Data Output Value bits
Note 1: See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-6: ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER⁽¹⁾
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
ODCx<15:8>
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
ODCx<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
ODCx<15:0>: PORTx Open-Drain Enable bits
1 = Open-drain is enabled on the PORTx pin
0 = Open-drain is disabled on the PORTx pin
Note 1: See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
 2016 Microchip Technology Inc.
DS30010118B-page 131