PIC24FJ64GA705 Datasheet, PDF (330/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 29-1: FSEC CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
R/PO-1
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
AIVTDIS
—
—
—
CSS2
CSS1
CSS0
CWRP
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
GSS1
GSS0
GWRP
—
BSEN
BSS1
BSS0
BWRP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
PO = Program Once bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-16
bit 15
bit 14-12
bit 11-9
bit 8
bit 7-6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Unimplemented: Read as ‘1’
AIVTDIS: Alternate Interrupt Vector Table Disable bit
1 = Disables AIVT; INTCON2<8> (AIVTEN) bit is not available
0 = Enables AIVT; INTCON2<8> (AIVTEN) bit is available
Unimplemented: Read as ‘1’
CSS<2:0>: Configuration Segment (CS) Code Protection Level bits
111 = No protection (other than CWRP)
110 = Standard security
10x = Enhanced security
0xx = High security
CWRP: Configuration Segment Program Write Protection bit
1 = Configuration Segment is not write-protected
0 = Configuration Segment is write-protected
GSS<1:0>: General Segment (GS) Code Protection Level bits
11 = No protection (other than GWRP)
10 = Standard security
0x = High security
GWRP: General Segment Program Write Protection bit
1 = General Segment is not write-protected
0 = General Segment is write-protected
Unimplemented: Read as ‘1’
BSEN: Boot Segment (BS) Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by BSLIM<12:0>
BSS<1:0>: Boot Segment Code Protection Level bits
11 = No protection (other than BWRP)
10 = Standard security
0x = High security
BWRP: Boot Segment Program Write Protection bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
DS30010118B-page 330
 2016 Microchip Technology Inc.