PIC24FJ64GA705 Datasheet, PDF (104/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 9-4: OSCDIV: OSCILLATOR DIVISOR REGISTER
U-0
—
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
DIV<14:8>
R/W-0
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
DIV<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-0
Unimplemented: Read as ‘0’
DIV<14:0>: Reference Clock Divider bits
Specifies the 1/2 period of the reference clock in the source clocks
(ex: Period of ref_clk_output = [Reference Source * 2] * DIV<14:0>).
111111111111111 = Oscillator frequency divided by 65,534 (32,767 * 2)
111111111111110 = Oscillator frequency divided by 65,532 (32,766 * 2)
•
•
•
000000000000011 = Oscillator frequency divided by 6 (3 * 2)
000000000000010 = Oscillator frequency divided by 4 (2 * 2)
000000000000001 = Oscillator frequency divided by 2 (1 * 2) (default)
000000000000000 = Oscillator frequency is unchanged (no divider)
DS30010118B-page 104
 2016 Microchip Technology Inc.