PIC24FJ64GA705 Datasheet, PDF (164/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 13-1: TxCON: TIMER2 CONTROL REGISTER⁽¹⁾
R/W-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
TON
—
TSIDL
—
—
—
TECS1⁽²⁾
TECS0⁽²⁾
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32⁽³⁾
—
TCS⁽²⁾
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6
bit 5-4
TON: Timerx On bit
When TxCON<3> = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When TxCON<3> = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
Unimplemented: Read as ‘0’
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
TECS<1:0>: Timerx Extended Clock Source Select bits (selected when TCS = 1)⁽²⁾
When TCS = 1:
11 = Generic timer (TxCK) external input
10 = LPRC Oscillator
01 = TyCK external clock input
00 = SOSC
When TCS = 0:
These bits are ignored; the timer is clocked from the internal system clock (FOSC/2).
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
Note 1:
2:
3:
Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TxCK or TyCK) must be configured to
an available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
In 32-bit mode, the T3CON control bits do not affect 32-bit timer operation.
DS30010118B-page 164
 2016 Microchip Technology Inc.