PIC24FJ64GA705 Datasheet, PDF (92/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 8-2:
U-0
—
bit 15
CORCON: CPU CORE CONTROL REGISTER⁽¹⁾
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
U-0
—
—
bit 8
U-0
—
bit 7
U-0
U-0
U-0
R/C-0
R/W-1
U-0
U-0
—
—
—
IPL3⁽²⁾
PSV
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’= Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit⁽²⁾
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
PSV: Not used as part of the interrupt module
Unimplemented: Read as ‘0’
Note 1:
2:
For complete register details, see Register 3-2.
The IPL<2:0> Status bits are concatenated with the IPL3 Status bit (CORCON<3>) to form the CPU
Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts
are disabled when IPL3 = 1.
DS30010118B-page 92
 2016 Microchip Technology Inc.