PIC24FJ64GA705 Datasheet, PDF (130/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 11-3: TRISx: OUTPUT ENABLE FOR PORTx REGISTER⁽¹⁾
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
TRISx<15:8>
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
TRISx<7:0>
R/W-1
R/W-1
R/W-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
TRISx<15:0>: Output Enable for PORTx bits
1 = LATx[n] is not driven on the PORTx[n] pin
0 = LATx[n] is driven on the PORTx[n] pin
Note 1: See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-4: PORTx: INPUT DATA FOR PORTx REGISTER⁽¹⁾
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
PORTx<15:8>
R/W-1
R/W-1
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
PORTx<7:0>
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
PORTx<15:0>: PORTx Data Input Value bits
Note 1: See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
DS30010118B-page 130
 2016 Microchip Technology Inc.