PIC24FJ64GA705 Datasheet, PDF (43/412 Pages) –

PIC24FJ256GA705 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
4.1.2 HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the PC
on a device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
The PIC24FJ256GA705 devices can have up to two
Interrupt Vector Tables (IVT). The first is located from
addresses, 000004h to 0000FFh. The Alternate Inter-
rupt Vector Table (AIVT), which can be enabled by the
AIVTDIS Configuration bit, is located from 000104h to
0001FFh if no Boot Segment (BS) is present. If the user
has configured a Boot Segment, the AIVT will be
located at the address, (BSLIM<12:0> x 1024) – 508.
These vector tables allow each of the many device
interrupt sources to be handled by separate Interrupt
Service Routines (ISRs). A more detailed discussion of
the Interrupt Vector Tables is provided in Section 8.1
“Interrupt Vector Table”.
4.1.3 CONFIGURATION BITS OVERVIEW
The Configuration bits are stored in the last page loca-
tion of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system oper-
ation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
Table 4-2 lists all of the Configuration registers as well
as their Configuration register locations. Refer to
Section 29.0 “Special Features” for the full
Configuration register description for each specific
device.
TABLE 4-2: CONFIGURATION WORD ADDRESSES
Configuration
Registers
PIC24FJ256GA70X
PIC24FJ128GA70X
FSEC
FBSLIM
FSIGN
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDEVOPT1
02AF00h
02AF10h
02AF14h
02AF18h
02AF1Ch
02AF20h
02AF24h
02AF28h
02AF2Ch
015F00h
015F10h
015F14h
015F18h
015F1Ch
015F20h
015F24h
015F28h
015F2Ch
PIC24FJ64GA70X
00AF00h
00AF10h
00AF14h
00AF18h
00AF1Ch
00AF20h
00AF24h
00AF28h
00AF2Ch
 2016 Microchip Technology Inc.
DS30010118B-page 43