PIC24FJ64GA705 Datasheet, PDF (198/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-7: CCPxSTATL: CCPx STATUS REGISTER LOW
U-0
U-0
U-0
U-0
U-0
W-0
U-0
—
—
—
—
—
ICGARM
—
bit 15
U-0
—
bit 8
R-0
CCPTRIG
bit 7
W1-0
TRSET
W1-0
TRCLR
R/C-0
ASEVT
R/C-0
SCEVT
R/C-0
ICDIS
R/C-0
ICOV
R/C-0
ICBNE
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W1 = Write ‘1’ Only bit
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ICGARM: Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when
ICGSM<1:0> = 01 or 10; read as ‘0’.
Unimplemented: Read as ‘0’
CCPTRIG: CCPx Trigger Status bit
1 = Timer has been triggered and is running
0 = Timer has not been triggered and is held in Reset
TRSET: CCPx Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1 (location always reads as ‘0’).
TRCLR: CCPx Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1 (location always reads as ‘0’).
ASEVT: CCPx Auto-Shutdown Event Status/Control bit
1 = A shutdown event is in progress; CCPx outputs are in the shutdown state
0 = CCPx outputs operate normally
SCEVT: Single Edge Compare Event Status bit
1 = A single edge compare event has occurred
0 = A single edge compare event has not occurred
ICDIS: Input Capture x Disable bit
1 = Event on Input Capture x pin (ICMx) does not generate a capture event
0 = Event on Input Capture x pin will generate a capture event
ICOV: Input Capture x Buffer Overflow Status bit
1 = The Input Capture x FIFO buffer has overflowed
0 = The Input Capture x FIFO buffer has not overflowed
ICBNE: Input Capture x Buffer Status bit
1 = Input Capture x buffer has data available
0 = Input Capture x buffer is empty
DS30010118B-page 198
 2016 Microchip Technology Inc.