PIC24FJ64GA705 Datasheet, PDF (195/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-4: CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS
R/W-0
U-0
OENSYNC
—
bit 15
R/W-0
OCFEN
R/W-0
OCEEN
R/W-0
OCDEN
R/W-0
OCCEN
R/W-0
ICGSM1
bit 7
R/W-0
ICGSM0
U-0
R/W-0
R/W-0
R/W-0
—
AUXOUT1 AUXOUT0
ICS2
R/W-0
OCBEN
R/W-0
ICS1
R/W-1
OCAEN
bit 8
R/W-0
ICS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-8
bit 7-6
bit 5
bit 4-3
bit 2-0
OENSYNC: Output Enable Synchronization bit
1 = Update by output enable bits occurs on the next Time Base Reset or rollover
0 = Update by output enable bits occurs immediately
Unimplemented: Read as ‘0’
OCxEN: Output Enable/Steering Control bits
1 = OCMx pin is controlled by the CCPx module and produces an output compare or PWM signal
0 = OCMx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
ICGSM<1:0>: Input Capture Gating Source Mode Control bits
11 = Reserved
10 = One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01 = One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00 = Level-Sensitive mode: A high level from gating source will enable future capture events; a low
level will disable future capture events
Unimplemented: Read as ‘0’
AUXOUT<1:0>: Auxiliary Output Signal on Event Selection bits
11 = Input capture or output compare event; no signal in Timer mode
10 = Signal output is defined by module operating mode (see Table 16-4)
01 = Time base rollover event (all modes)
00 = Disabled
ICS<2:0>: Input Capture Source Select bits
111 = Reserved
110 = Reserved
101 = CLC2 output
100 = CLC1 output
011 = Comparator 3 output
010 = Comparator 2 output
001 = Comparator 1 output
000 = Input Capture x (ICMx) I/O pin
 2016 Microchip Technology Inc.
DS30010118B-page 195