PIC24FJ64GA705 Datasheet, PDF (170/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
R/W-0
IC32
bit 8
R/W-0
ICTRIG
bit 7
R/W-0, HS
TRIGSTAT
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
—
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 8
bit 7
bit 6
bit 5
Unimplemented: Read as ‘0’
IC32: Cascade Two Input Capture Modules Enable bit (32-bit operation)
1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules)
0 = ICx functions independently as a 16-bit module
ICTRIG: Input Capture x Sync/Trigger Select bit
1 = Triggers ICx from the source designated by the SYNCSELx bits
0 = Synchronizes ICx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running (set in hardware, can be set in software)
0 = Timer source has not been triggered and is being held clear
Unimplemented: Read as ‘0’
Note 1: Use these inputs as Trigger sources only and never as Sync sources.
2: Never use an Input Capture x module as its own Trigger source by selecting this mode.
DS30010118B-page 170
 2016 Microchip Technology Inc.