PIC24FJ64GA705 Datasheet, PDF (254/412 Pages) –

PIC24FJ256GA705 FAMILY
21.3 Registers
21.3.1 RTCC CONTROL REGISTERS
REGISTER 21-1: RTCCON1L: RTCC CONTROL REGISTER 1 (LOW)
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
RTCEN
—
—
—
WRLOCK
PWCEN
bit 15
R/W-0
PWCPOL
R/W-0
PWCPOE
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
RTCOE
OUTSEL2 OUTSEL1 OUTSEL0
—
—
—
TSAEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6-4
bit 3-1
bit 0
RTCEN: RTCC Enable bit
1 = RTCC is enabled and counts from selected clock source
0 = RTCC is not enabled
Unimplemented: Read as ‘0’
WRLOCK: RTCC Register Write Lock
1 = RTCC registers are locked
0 = RTCC registers may be written to by user
PWCEN: Power Control Enable bit
1 = Power control is enabled
0 = Power control is disabled
PWCPOL: Power Control Polarity bit
1 = Power control output is active-high
0 = Power control output is active-low
PWCPOE: Power Control Output Enable bit
1 = Power control output pin is enabled
0 = Power control output pin is disabled
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
OUTSEL<2:0>: RTCC Output Signal Selection bits
111 = Unused
110 = Unused
101 = Unused
100 = Timestamp A event
011 = Power control
010 = RTCC input clock
001 = Second clock
000 = Alarm event
Unimplemented: Read as ‘0’
TSAEN: Timestamp A Enable bit
1 = Timestamp event will occur when a low pulse is detected on the TMPRN pin
0 = Timestamp is disabled
DS30010118B-page 254
 2016 Microchip Technology Inc.