PIC24FJ64GA705 Datasheet, PDF (71/412 Pages) –

PIC24FJ256GA705 FAMILY
6.0 FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to
the “dsPIC33/PIC24 Family Reference
Manual”, “PIC24F Flash Program
Memory” (DS30009715), which is available
from the Microchip web site
(www.microchip.com). The information in
this data sheet supersedes the
information in the FRM.
The PIC24FJ256GA705 family of devices contains
internal Flash program memory for storing and execut-
ing application code. The program memory is readable,
writable and erasable. The Flash memory can be
programmed in four ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• JTAG
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24FJ256GA705 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (named PGCx and PGDx,
respectively), and three other lines for power (VDD),
ground (VSS) and Master Clear (MCLR). This allows
customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
may write program memory data in blocks of
128 instructions (384 bytes) at a time and erase
program memory in blocks of 1024 instructions
(3072 bytes) at a time.
The device implements a 7-bit Error Correcting Code
(ECC). The NVM block contains a logic to write and
read ECC bits to and from the Flash memory. The
Flash is programmed at the same time as the
corresponding ECC parity bits. The ECC provides
improved resistance to Flash errors. ECC single bit
errors can be transparently corrected; ECC double-bit
errors result in a trap.
6.1 Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG<7:0> bits and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 6-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 6-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program 0
Program Counter
0
Counter
Using
Table
1/0
Instruction
TBLPAG Reg
8 Bits
Working Reg EA
16 Bits
User/Configuration
Space Select
24-Bit EA
Byte
Select
 2016 Microchip Technology Inc.
DS30010118B-page 71