PIC24FJ64GA705 Datasheet, PDF (79/412 Pages) –

PIC24FJ256GA705 FAMILY
7.0 RESETS
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “dsPIC33/PIC24 Family Reference
Manual”, “Reset” (DS39712), which is
available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is
shown in Figure 7-1.
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A POR will clear all bits, except for
the BOR and POR (RCON<1:0>) bits, which are set.
The user may set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a particular Reset status bit in software will
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register values after a
device Reset will be meaningful.
FIGURE 7-1:
MCLR
VDD
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
WDT
Module
Sleep or Idle
VDD Rise
Detect
POR
Brown-out
Reset
BOR
SYSRST
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register
 2016 Microchip Technology Inc.
DS30010118B-page 79