PIC24FJ64GA705 Datasheet, PDF (15/412 Pages) –

PIC24FJ256GA705 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA705
• PIC24FJ256GA704
• PIC24FJ128GA705 • PIC24FJ64GA702
• PIC24FJ256GA705 • PIC24FJ128GA702
• PIC24FJ64GA704
• PIC24FJ256GA702
• PIC24FJ128GA704
The PIC24FJ256GA705 family introduces large Flash
and SRAM memory in smaller package sizes. This is a
16-bit microcontroller family with a broad peripheral
feature set and enhanced computational performance.
This family also offers a new migration option for those
high-performance applications which may be outgrow-
ing their 8-bit platforms, but do not require the numerical
processing power of a Digital Signal Processor (DSP).
Table 1-3 lists the functions of the various pins shown
in the pinout diagrams.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC^® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements,
such as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2 POWER-SAVING TECHNOLOGY
The PIC24FJ256GA705 family of devices includes
Retention Sleep, a low-power mode with essential
circuits being powered from a separate low-voltage
regulator.
This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.
Aside from this new feature, PIC24FJ256GA705 family
devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and Sleep modes
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ256GA705 family offer
six different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes
• External Clock (EC) mode
• A Phase-Locked Loop (PLL) frequency multiplier,
which allows processor speeds up to 32 MHz
• An internal Fast RC Oscillator (FRC), a nominal
8 MHz output with multiple frequency divider
options
• A separate internal Low-Power RC Oscillator
(LPRC), 31 kHz nominal for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device.
The PIC24F family is pin-compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
 2016 Microchip Technology Inc.
DS30010118B-page 15