PIC24FJ64GA705 Datasheet, PDF (204/412 Pages) –

PIC24FJ256GA705 FAMILY
17.4 SPI Control Registers
REGISTER 17-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW
R/W-0
SPIEN
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SPISIDL
DISSDO MODE32^(1,4) MODE16^(1,4)
R/W-0
SMP
R/W-0
CKE⁽¹⁾
bit 8
R/W-0
SSEN⁽²⁾
bit 7
R/W-0
CKP
R/W-0
MSTEN
R/W-0
DISSDI
R/W-0
DISSCK
R/W-0
MCLKEN⁽³⁾
R/W-0
SPIFE
R/W-0
ENHBUF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11-10
bit 9
SPIEN: SPIx On bit
1 = Enables module
0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
Unimplemented: Read as ‘0’
SPISIDL: SPIx Stop in Idle Mode bit
1 = Halts in CPU Idle mode
0 = Continues to operate in CPU Idle mode
DISSDO: Disable SDOx Output Port bit
1 = SDOx pin is not used by the module; pin is controlled by the port function
0 = SDOx pin is controlled by the module
MODE<32,16>: Serial Word Length bits^(1,4)
AUDEN = 0:
MODE32 MODE16 COMMUNICATION
1
x
0
1
0
0
32-Bit
16-Bit
8-Bit
AUDEN = 1:
MODE32
1
1
0
0
MODE16
1
0
1
0
COMMUNICATION
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
SMP: SPIx Data Input Sample Phase bit
Master Mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave Mode:
Input data is always sampled at the middle of data output time, regardless of the SMP setting.
Note 1:
2:
3:
4:
When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
When FRMEN = 1, SSEN is not used.
MCLKEN can only be written when the SPIEN bit = 0.
This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
DS30010118B-page 204
 2016 Microchip Technology Inc.