PIC24FJ64GA705 Datasheet, PDF (162/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 13-1:
TIMER2/3 (32-BIT) BLOCK DIAGRAM
T2CK
TxCK
SOSC Input
LPRC Input
TCY
Gate
Sync
TGATE
1
Set T3IF
0
TECS<1:0>
QD
Q CK
PR3
PR2
TGATE⁽²⁾
TCS⁽²⁾
A/D Event Trigger⁽³⁾
Equal
Comparator
MSB
LSB
Reset
TMR3
16
Read TMR2⁽¹⁾
Write TMR2⁽¹⁾
16
TMR3HLD
TMR2
16
Sync
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
Data Bus<15:0>
Note 1:
2:
3:
The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON register.
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5
“Peripheral Pin Select (PPS)” for more information.
The A/D event trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode.
DS30010118B-page 162
 2016 Microchip Technology Inc.