PIC24FJ64GA705 Datasheet, PDF (175/412 Pages) –

PIC24FJ256GA705 FAMILY
For 32-bit cascaded operation, these steps are also
necessary:
1. Set the OC32 bits for both registers
(OCyCON2<8> and OCxCON2<8>). Enable the
even numbered module first to ensure the
modules will start functioning in unison.
2. Clear the OCTRIG bit of the even module
(OCyCON2<7>), so the module will run in
Synchronous mode.
3. Configure the desired output and Fault settings
for OCy.
4. Force the output pin for OCx to the output state
by clearing the OCTRIS bit.
5. If Trigger mode operation is required, configure
the Trigger options in OCx by using the OCTRIG
(OCxCON2<7>), TRIGMODE (OCxCON1<3>)
and SYNCSEL<4:0> (OCxCON2<4:0>) bits.
6. Configure the desired Compare or PWM mode
of operation (OCM<2:0>) for OCy first, then for
OCx.
Depending on the output mode selected, the module
holds the OCx pin in its default state and forces a tran-
sition to the opposite state when OCxR matches the
timer. In Double Compare modes, OCx is forced back
to its default state when a match with OCxRS occurs.
The OCxIF interrupt flag is set after an OCxR match in
Single Compare modes and after each OCxRS match
in Double Compare modes.
Single-Shot pulse events only occur once, but may be
repeated by simply rewriting the value of the
OCxCON1 register. Continuous pulse events continue
indefinitely until terminated.
15.3 Pulse-Width Modulation (PWM)
Mode
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are double-
buffered (buffer registers are internal to the module and
are not mapped into SFR space).
To configure the output compare module for PWM
operation:
1. Configure the OCx output for one of the
available Peripheral Pin Select pins if available
on the OC module you are using. Otherwise,
configure the dedicated OCx output pins.
2. Calculate the desired duty cycles and load them
into the OCxR register.
3. Calculate the desired period and load it into the
OCxRS register.
4. Select the current OCx as the synchronization
source by writing ‘0x1F’ to the SYNCSEL<4:0>
bits (OCxCON2<4:0>) and ‘0’ to the OCTRIG bit
(OCxCON2<7>).
5. Select a clock source by writing to the
OCTSEL<2:0> bits (OCxCON1<12:10>).
6. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin
utilization.
7. Select the desired PWM mode in the OCM<2:0>
bits (OCxCON1<2:0>).
8. Appropriate Fault inputs may be enabled by
using the ENFLT<2:0> bits as described in
Register 15-1.
9. If a timer is selected as a clock source, set the
selected timer prescale value. The selected
timer’s prescaler output is used as the clock
input for the OCx timer and not the selected
timer output.
Note:
This peripheral contains input and output
functions that may need to be configured
by the Peripheral Pin Select. See
Section 11.5 “Peripheral Pin Select
(PPS)” for more information.
 2016 Microchip Technology Inc.
DS30010118B-page 175