PIC24FJ64GA705 Datasheet, PDF(181/412 Page) –

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PIC24FJ64GA705 Datasheet, PDF (181/412 Pages) –

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PIC24FJ256GA705 FAMILY

REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)

bit 4-0

SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits

11111 = OCx Sync out(1)

11110 = OCTRIG1 pin

11101 = OCTRIG2 pin

11100 = CTMU trigger(2)

11011 = A/D interrupt(2)

11010 = CMP3 Trigger(2)

11001 = CMP2 Trigger(2)

11000 = CMP1 Trigger(2)

10111 = Not used

10110 = MCCP4 IC/OC interrupt

10101 = MCCP3 IC/OC interrupt

10100 = MCCP2 IC/OC interrupt

10011 = MCCP1 IC/OC interrupt

10010 = IC3 interrupt(2)

10001 = IC2 interrupt(2)

10000 = IC1 interrupt(2)

01111 = Not used

01110 = Not used

01101 = Timer3 match event

01100 = Timer2 match event (default)

01011 = Timer1 match event

01010 = Not used

01001 = Not used

01000 = Not used

00111 = MCCP4 Sync/Trigger out

00110 = MCCP3 Sync/Trigger out

00101 = MCCP2 Sync/Trigger out

00100 = MCCP1 Sync/Trigger out

00011 = Not used

00010 = OC3 Sync/Trigger out(1)

00001 = OC1 Sync/Trigger out(1)

00000 = Off, Free-Running mode with no synchronization and rollover at FFFFh

Note 1:

2:

3:

Never use an Output Compare x module as its own Trigger source, either by selecting this mode or

another equivalent SYNCSELx setting.

Use these inputs as Trigger sources only and never as Sync sources.

The DCB<1:0> bits are double-buffered in the PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).

ï£ 2016 Microchip Technology Inc.

DS30010118B-page 181

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