PIC24FJ64GA705 Datasheet, PDF (215/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 17-10: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH
R/W-0
RXWIEN
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
RXMSK5⁽¹⁾ RXMSK4^(1,4) RXMSK3^(1,3) RXMSK2^(1,2)
R/W-0
RXMSK1⁽¹⁾
R/W-0
RXMSK0⁽¹⁾
bit 8
R/W-0
TXWIEN
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TXMSK5⁽¹⁾ TXMSK4^(1,4) TXMSK3^(1,3) TXMSK2^(1,2) TXMSK1⁽¹⁾ TXMSK0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-8
bit 7
bit 6
bit 5-0
RXWIEN: Receive Watermark Interrupt Enable bit
1 = Triggers receive buffer element watermark interrupt when RXMSK<5:0>  RXELM<5:0>
0 = Disables receive buffer element watermark interrupt
Unimplemented: Read as ‘0’
RXMSK<5:0>: RX Buffer Mask bits^(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
TXWIEN: Transmit Watermark Interrupt Enable bit
1 = Triggers transmit buffer element watermark interrupt when TXMSK<5:0> = TXELM<5:0>
0 = Disables transmit buffer element watermark interrupt
Unimplemented: Read as ‘0’
TXMSK<5:0>: TX Buffer Mask bits^(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.
Note 1:
2:
3:
4:
Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in
this case.
RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.
 2016 Microchip Technology Inc.
DS30010118B-page 215