PIC24FJ64GA705 Datasheet, PDF (309/412 Pages) –

PIC24FJ256GA705 FAMILY
25.0 TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“dsPIC33/PIC24 Family Reference Man-
ual”, “Scalable Comparator Module”
(DS39734), which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and CVREF+) and a
voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG and CVREF).
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE bit equals
‘1’, the I/O pad logic makes the unsynchronized output
of the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 25-1. Diagrams of the possible individual
comparator configurations are shown in Figure 25-2
through Figure 25-4.
Each comparator has its own control register,
CMxCON (Register 25-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 25-2).
FIGURE 25-1:
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
CCH<1:0>
CxINB
CxINC
CxIND
VBG
CVREF+
CVREFM<1:0>⁽¹⁾
Input
Select
Logic
00
01
10
11
00
VIN-
VIN+ ^C1
–
11
VIN-
VIN+ ^C2
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C1OUT
COUT ^Pin
CEVT
COE
C2OUT
Pin
COUT
CxINA
Comparator Voltage
Reference
CVREF+
CVREFP⁽¹⁾
CREF
0
+
0
1
1
VIN-
VIN+ ^C3
EVPOL<1:0>
CPOL
Trigger/Interrupt
Logic
CEVT
COE
C3OUT
COUT ^Pin
Note 1: Refer to the CVRCON register (Register 26-1) for bit details.
 2016 Microchip Technology Inc.
DS30010118B-page 309