PIC24FJ64GA705 Datasheet, PDF (211/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 17-5: SPIxSTATH: SPIx STATUS REGISTER HIGH
U-0
—
bit 15
U-0
R-0, HSC
R-0, HSC
R-0, HSC
—
RXELM5⁽³⁾
RXELM4⁽²⁾
RXELM3⁽¹⁾
R-0, HSC
RXELM2
R-0, HSC
RXELM1
R-0, HSC
RXELM0
bit 8
U-0
—
bit 7
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC R-0, HSC R-0, HSC
—
TXELM5⁽³⁾
TXELM4⁽²⁾
TXELM3⁽¹⁾
TXELM2
TXELM1
TXELM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RXELM<5:0>: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)^(1,2,3)
Unimplemented: Read as ‘0’
TXELM<5:0>: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)^(1,2,3)
Note 1:
2:
3:
RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.
 2016 Microchip Technology Inc.
DS30010118B-page 211