PIC24FJ64GA705 Datasheet, PDF (301/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 24-7: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
U-0
—
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
VBGEN3⁽¹⁾ VBGEN2⁽¹⁾ VBGEN1⁽¹⁾
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
VBGEN3: A/D Band Gap Reference Enable bit⁽¹⁾
1 = Band gap reference is enabled
0 = Band gap reference is disabled
VBGEN2: CTMU and Comparator Band Gap Reference Enable bit⁽¹⁾
1 = Band gap reference is enabled
0 = Band gap reference is disabled
VBGEN1: VREG, BOR, HLVD, FRC, NVM and A/D Boost Band Gap Reference Enable bit⁽¹⁾
1 = Band gap reference is enabled
0 = Band gap reference is disabled
Note 1: When a module requests a band gap reference voltage, that reference will be enabled automatically after
a brief start-up time. The user can manually enable the band gap references using the ANCFG register
before enabling the module requesting the band gap reference to avoid this start-up time (~1 ms).
 2016 Microchip Technology Inc.
DS30010118B-page 301