PIC24FJ64GA705 Datasheet, PDF (207/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 17-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED)
bit 6
bit 5
bit 4
bit 3
bit 2-0
FRMSYNC: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
FRMPOL: Frame Sync/Slave Select Polarity bit
1 = Frame Sync pulse/slave select is active-high
0 = Frame Sync pulse/slave select is active-low
MSSEN: Master Mode Slave Select Enable bit
1 = SPIx slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically
driven during transmission in Master mode)
0 = SPIx slave select support is disabled (SSx pin will be controlled by port IO)
FRMSYPW: Frame Sync Pulse-Width bit
1 = Frame Sync pulse is one serial word length wide (as defined by MODE<32,16>/WLENGTH<4:0>)
0 = Frame Sync pulse is one clock (SCK) wide
FRMCNT<2:0>: Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
111 = Reserved
110 = Reserved
101 = Generates a Frame Sync pulse on every 32 serial words
100 = Generates a Frame Sync pulse on every 16 serial words
011 = Generates a Frame Sync pulse on every 8 serial words
010 = Generates a Frame Sync pulse on every 4 serial words
001 = Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000 = Generates a Frame Sync pulse on each serial word
Note 1:
2:
3:
4:
AUDEN can only be written when the SPIEN bit = 0.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
URDTEN is only valid when IGNTUR = 1.
AUDMOD<1:0> bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1.
When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
 2016 Microchip Technology Inc.
DS30010118B-page 207