PIC24FJ64GA705 Datasheet, PDF (244/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 20-3: PMCON3: EPMP CONTROL REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
U-0
PTWREN PTRDEN PTBE1EN PTBE0EN
—
bit 15
R/W-0
AWAITM1
R/W-0
AWAITM0
R/W-0
AWAITE
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7-0
PTWREN: Write/Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
PTBE1EN: High Nibble/Byte Enable Port Enable bit
1 = PMBE1 port is enabled
0 = PMBE1 port is disabled
PTBE0EN: Low Nibble/Byte Enable Port Enable bit
1 = PMBE0 port is enabled
0 = PMBE0 port is disabled
Unimplemented: Read as ‘0’
AWAITM<1:0>: Address Latch Strobe Wait State bits
11 = Wait of 3½ TCY
10 = Wait of 2½ TCY
01 = Wait of 1½ TCY
00 = Wait of ½ TCY
AWAITE: Address Hold After Address Latch Strobe Wait State bits
1 = Wait of 1¼ TCY
0 = Wait of ¼ TCY
Unimplemented: Read as ‘0’
DS30010118B-page 244
 2016 Microchip Technology Inc.