PIC24FJ64GA705 Datasheet, PDF (202/412 Pages) –

PIC24FJ256GA705 FAMILY
17.1 Master Mode Operation
Perform the following steps to set up the SPIx module
for Master mode operation:
1. Disable the SPIx interrupts in the respective
IECx register.
2. Stop and reset the SPIx module by clearing the
SPIEN bit.
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON1L<0>) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
5. If SPIx interrupts are not going to be used, skip
this step. Otherwise, the following additional
steps are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
6. Write the Baud Rate register, SPIxBRGL.
7. Clear the SPIROV bit (SPIxSTATL<6>).
8. Write the desired settings to the SPIxCON1L
register with MSTEN (SPIxCON1L<5>) = 1.
9. Enable SPI operation by setting the SPIEN bit
(SPIxCON1L<15>).
10. Write the data to be transmitted to the
SPIxBUFL and SPIxBUFH registers. Transmis-
sion (and reception) will start as soon as data is
written to the SPIxBUFL/H registers.
17.2 Slave Mode Operation
The following steps are used to set up the SPIx module
for the Slave mode of operation:
1. If using interrupts, disable the SPIx interrupts in
the respective IECx register.
2. Stop and reset the SPIx module by clearing the
SPIEN bit.
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON1L<0>) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
5. If using interrupts, the following additional steps
are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
6. Clear the SPIROV bit (SPIxSTATL<6>).
7. Write the desired settings to the SPIxCON1L
register with MSTEN (SPIxCON1L<5>) = 0.
8. Enable SPI operation by setting the SPIEN bit
(SPIxCON1L<15>).
9. Transmission (and reception) will start as soon
as the master provides the serial clock.
The following additional features are provided in
Slave mode:
• Slave Select Synchronization:
The SSx pin allows a Synchronous Slave mode. If
the SSEN bit (SPIxCON1L<7>) is set, transmis-
sion and reception are enabled in Slave mode
only if the SSx pin is driven to a low state. The
port output or other peripheral outputs must not
be driven in order to allow the SSx pin to function
as an input. If the SSEN bit is set and the SSx pin
is driven high, the SDOx pin is no longer driven
and will tri-state, even if the module is in the
middle of a transmission. An aborted transmission
will be tried again the next time the SSx pin is
driven low using the data held in the SPIxTXB
register. If the SSEN bit is not set, the SSx pin
does not affect the module operation in Slave
mode.
• SPITBE Status Flag Operation:
The SPITBE bit (SPIxSTATL<3>) has a different
function in the Slave mode of operation. The
following describes the function of SPITBE for
various settings of the Slave mode of operation:
- If SSEN (SPIxCON1L<7>) is cleared, the
SPITBE bit is cleared when SPIxBUF is
loaded by the user code. It is set when the
module transfers SPIxTXB to SPIxTXSR.
This is similar to the SPITBE bit function in
Master mode.
- If SSEN is set, SPITBE is cleared when
SPIxBUF is loaded by the user code. How-
ever, it is set only when the SPIx module
completes data transmission. A transmission
will be aborted when the SSx pin goes high
and may be retried at a later time. So, each
data word is held in SPIxTXB until all bits are
transmitted to the receiver.
DS30010118B-page 202
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