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PIC24FJ64GA705 Datasheet, PDF (233/412 Pages) – | |||
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PIC24FJ256GA705 FAMILY
REGISTER 19-1: UxMODE: UARTx MODE REGISTER
R/W-0
U-0
UARTEN(1)
â
bit 15
R/W-0
R/W-0
R/W-0
U-0
USIDL
IREN(2)
RTSMD
â
R/W-0
UEN1
R/W-0
UEN0
bit 8
R/W-0, HC
WAKE
bit 7
R/W-0
LPBACK
R/W-0, HC
ABAUD
R/W-0
URXINV
R/W-0
BRGH
R/W-0
PDSEL1
R/W-0
PDSEL0
R/W-0
STSEL
bit 0
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
W = Writable bit
U = Unimplemented bit, read as â0â
â1â = Bit is set
â0â = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal
Unimplemented: Read as â0â
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
Unimplemented: Read as â0â
UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
port latches
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character â requires reception of a Sync field (55h);
cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is â0â
0 = UxRX Idle state is â1â
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 âPeripheral Pin Select (PPS)â.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
ï£ 2016 Microchip Technology Inc.
DS30010118B-page 233
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